The option “Inverted” or “overline” is helpful to tag pins with inverted input: it places a bar on top of the
name.
The option “Rectangle” draws a bounding rectangle using the geometry of your original mouse selection area.
This bounding rectangle cannot be changed without recreating the annotation.
By selecting multiple annotations from the list on the left, you can modify them all at once; for example, you
can set the text size or one of the positions of several annotations to the same value.
You can have more than one set of annotations. While the default set loads on the application startup
(“annotations.json”), you can drag and drop a file containing another set of annotations onto the Image View.
Any edits will be saved back to that file. For example, “annot_internals.json” is an example of another
annotation file: it contains markups of features that are less abstract than the default annotations file.
The annotation text also supports macros, which are simple substitutions of named nets and buses for their
value. Anywhere in the annotation text, you can refer to a net or a bus, enclose its name with a set of curly
brackets (for example: “{DBUS}”), and the annotation shows its current value.
A resource file, “annot_functional.json,” is an example of such a ‘functional’ annotation showing the runtime
values of all major buses and latches.
Since all internal data buses in Z80 carry inverted values, an option was added to invert the value of a net/bus
when you add tilde ~ in front of a name, as in “{~VBUS}”. The value displayed is inverted, and a symbol ~ is
shown to make that unambiguous. This output format is consistent with the Waveform View’s “Ones’
Complement” format.
Schematic View
This option shows the net schematic. At this time, it is experimental and far from perfect; it is a work in
progress. The selected net is traced back to all the nets contributing to its state. This traversal ends with
certain terminating nets, which are chosen as reasonably good endpoints:
• Power, ground, and clock networks
• PLA signals
• Internal buses (ab, db, ubus, vbus)
• A few predefined nets like “int_reset” (internal reset signal)
• Detected and custom-defined latches
In addition, the traversal ends when a contributing net has already been processed to prevent possibly infinite
loops. The leaf nodes display their tip text (if defined).